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general description the max8904 power-management ic provides a com-plete power-supply solution for 2-cell li+ handheld/li-poly applications such as point-of-sale terminals, digital slr cameras, digital video cameras and ultra-mobile pcs. the max8904 includes five step-down converters (1v2, 1v8, 3v3, 5v0, and adj) with internal mosfets and +1%/-3% accurate output voltages for processor core, memory, i/o, and other system power rail requirements. lcd backlighting is supported by a wled boost con- verter that can provide 35ma for up to 8 wleds. this boost converter is also configurable as a 6-bit program- mable voltage source that can provide up to 63ma of output current. a 500ma, internal mosfet, current-lim- ited switch (cls), allows system designers to control input power to external peripheral devices. the max8904 controls an external n-mosfet for input overvoltage protection (13.5v, typ) and an external p-mosfet for reverse polarity protection (up to -28v) of downstream circuits. system input current monitoring for power management is facilitated by an on-board current-sense amplifier (csa) with differential inputs and a 1.2v full scale, ground-referenced analog output. a 400khz, i 2 c interface supports output voltage setting of the adj power rail and boost regulator (voltagesource mode), wled current setting for the boost regu- lator (wled current regulator mode), gpio control, and enable/disable of adj, 5v0, boost regulator, csa blocks. the i 2 c interface also enables the host proces- sor to read on-board fault status registers when inter-rupted by the max8904 flt pin under system fault conditions.an emergency shutdown input, shdn allows convert- ers preselected through i 2 c to turn off immediately under power-fail conditions, thus saving valuablefirmware execution time. an uncommitted, active-low, 14v open-drain comparator (cmp) with a 1.25v internal reference is also provided in the max8904. the max8904 pwren logic input turns on the 1v2, 1v8, 3v3, and 5v0 default power rails. the max8904 is available in a 56-pin, 7mm x 7mm tqfn package. applications point-of-sale terminalsdigital video cameras digital slr cameras ultra-mobile pcs features ? 3.4v to 13.2v input voltage range ? 1mhz, up to 90% efficient, synchronous dc-dcstep-down converters ? power converters 1v2, 1v8, and adj operatedout-of-phase with respect to 3v3 and 5v0 ? 667khz step-up converter provides up to 32voutput for driving up to eight wleds ? internal compensation on all power converters ? fast line and load transient responses ? internal soft-start and short-circuit protection onall power converter outputs ? input overvoltage and reverse polarity protection ? 250ms fault timer-based protection for overload,short circuit ? i 2 c serial interface for on/off control, output voltage, wled current, gpio setting, faultmonitoring ? < 15? standby current over operating voltagerange and temperature ? compact, 56-pin, 7mm x 7mm tqfn package max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ________________________________________________________________ maxim integrated products 1 19-4497; rev 0; 7/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. ordering information part temp range pin-package max8904etn+t -40c to +85c 56 thin qfn-ep* (7mm x 7mm) pin configuration appears at end of data sheet. 1.2v, 600ma 1.8v, 975ma 1ma to 63ma up to 8 wleds cs- bstlx sda cs+ 8-bit gpio port 1v2lx 1v8lx adjlx2 gpio7 gpio0 pcs ovgate v in scl pwren shdn flt lvrout lvrin5v rpgate lvrpwr ovpwr 3v3lx5v0lx adjlx1 3.3v, 1250ma 5v, 800ma 3.0v to 5.067v, 1500ma gnd cmpicmpo v in v in clsinclsout csout v ext v in max8904 typical operating circuit downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics (v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ovpwr to gnd......................................................-0.3v to +30v rpgate to gnd.....................................................-0.3v to +17v ovpwr to rpgate................................................-0.3v to +22v ovgate to cs+ .......................................................-0.3v to +6v bstfb to gnd........................................................-0.3v to +40v bstlx to exposed pad (ep) ..................................-0.3v to +40v bstsw to bstin ....................................................-16v to +0.3v lvrpwr, bstin, bstsw, 1v2in, 3v3in, 1v8in, adjin, 5v0in, cmpo , clsin to ep...............................-0.3v to +16v gpio_ to ep..............................................................-0.3v to +6v cs+, cs- to gnd ...................................................-0.3v to +16v cs+ to cs- ............................................................-0.3v to +0.3v clsout to gnd ....................................-0.3v to (v clsin + 0.3v) lvrout to gnd.................................-0.3v to (v lvrpwr + 0.3v) 1v2fb, 1v8fb, 3v3fb, 5v0fb, adjfb, ref, csout, cmpi to gnd .................................-0.3v to (v lvrin5v + 0.3v) 1v2bst to 1v2lx, 1v8bst to 1v8lx, 3v3bst to 3v3lx, 5v0bst to 5v0lx, adjbst to adjlx_................-0.3v to +6v lvrin5v, lvrout, shdn , pwren, flt , sda, scl, gpiopwr to gnd ...............................................-0.3v to +6v pcs to gnd ...........................................-0.3v to (v bstin + 0.3v) ep to gnd .............................................................-0.3v to +0.3v gpiopwr to lvrin5v..............................................-6v to +0.3v lvrout to lvrin5v .............................................-0.3v to +0.3v adjlx_, 5v0lx, 3v3lx, 1v8lx, 1v2lx, bstlx (note 1)........................................................?.7a rms continuous power dissipation (t a = +70?) 56-pin tqfn-ep single-layer pcb (derate 27.8mw/? above +70?) ............................2222mw 56-pin tqfn-ep multilayer pcb (derate 40mw/? above +70?) ...............................3200mw junction-to-case thermal resistance ( jc ) (note 2) .....0.8?/w junction-to-ambient thermal resistance ( ja ) (note 2) single-layer pcb ........................................................36?/w multilayer pcb .............................................................25?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units common blocks v _in falling, ovp circuit not used 3.6 14 v _in rising, ovp circuit not used 5.8 14 v _in falling, ovp circuit used 3.6 12.8 input operating supply range v _in v _in rising, ovp circuit used 5.8 13.2 v input standoff voltage v ovpwr 28 v standby mode supply current i _in + i lvrpwr + i cs_ v _in = 13.2v; all channels off 5.5 ? quiescent supply current(ch7 + ch2 + ch3 + ch4 only) ? i qlvrpwr + i 1v2in + i 1v8in + i 3v3in + i 5v0in + i 5v0fb no switching, v 1v2fb = 1.3v, v 1v8fb = 1.9v, v 3v3fb = 3.4v, v 5v0fb = 5.1v 100 165 ? note 1: _lx pins have internal clamp diodes to _in and ep. applications that forward bias these diodes should take care not to exceed the device? power-dissipation limits. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layerboard. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units i ref = 0? 1.240 1.250 1.260 ref output voltage v ref i ref = 10? 1.249 v osc frequency f osc 0.9 1 1.1 mhz lvrout output voltage 5.4v < v lvrpwr < 14v 4.9 5.1 5.3 v v lvrpwr rising 5.3 5.55 5.8 lvrpwr undervoltage lockoutthreshold v lvrpwr falling 3.2 3.4 3.6 v v lvrin5v rising 3.45 lvrin5v undervoltage lockoutthreshold v lvrin5v falling 2.6 v shdn input high voltage v ih 3v < v lvrin5v < 5.5v 1.6 v shdn input low voltage v il 3v < v lvrin5v < 5.5v 0.5 v s hd n p ul l up resi stance to lv rin 5v 1m shdn pulldown resistance to gnd 2m pwren input high voltage v ih 3.4v < v lvrpwr < 14v 1.6 v pwren input low voltage v il 3.4v < v lvrpwr < 14v 0.5 v pwren pulldown resistance 1m pwren deglitch delay rising 10 ? flt output-voltage low v flt i flt = 20ma 0 0.4 v t a = +25? 0.01 0.1 flt open-drain leakage current v flt = 5.5v t a = +85? 0.1 ? fault timer delay t fault 250 ms overtemperature warning flag rising (note 3) (bit d3 of register 0dh) 110 120 130 ? overtemperature warning flaghysteresis 10 ? thermal shutdown latchthreshold (note 3) 140 152 165 ? input voltage protection v ovpwr rising 3.75 4 4.25 ovpwr undervoltage lockoutthreshold v ovpwr falling 2.7 2.85 3.0 v ovpwr_uvlo_rising toovgate startup delay t startup v ovpwr > v ovpwr_uvlo_rising 32 ms v ovpwr rising 13.3 13.65 14 ovp threshold v ovp hysteresis 0.17 v ovgate charge current i ov gate _c h g v ovgate = 7.2v 10 ? ovgate discharge resistance r dchg v cs+ = 14.1v, v ovgate = 15.1v 40 rpgate pulldown resistor r rpgate 50 k rpgate clamp voltage v clamp 14v v ovpwr 28v 16 19 v electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 4 _______________________________________________________________________________________ electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units ch1 (current-limited switch) current-limited switchon-resistance r oncls i cls = 400ma 200 300 425 m _ current limit i limcls v clsin = 12v, v clsout = 9v 450 600 ma overcurrent fault latch-off delay t olflt 250 ms fault voltage v act v clsin - v clsout > 1v, 150mv hysteresis 1 v thermal loop threshold thm th current-limit-foldback temperature threshold (note 3) 110 120 130 ? t a = +25? 0.01 1 clsout leakage current i clsoutlkg v clsin = 14v, v clsout = 0 t a = +85? 0.1 ? ch2 (1v8 step-down converter) output voltage v 1v8fb no load 1.800 1.818 1.836 v operating frequency f 1v8lx 1 mhz load regulation -2.5 %/a line regulation v 1v8in = 3.4v to 14v 0.04 %/v idle-mode trip level (note 4) 150 ma t a = +25? -5 0.01 +5 1v8lx leakage current i 1v8lxlkg v 1v8lx = 0, 14v, v 1v8in = 14v t a = +85? 0.1 ? t a = +25c 0.01 0.1 1v8bst leakage current i 1v8bstlkg v 1v8bst = 5v + v 1v8in t a = +85c 0.1 ? low-side switch on-resistance r onls1v8 0.185 _ high-side switch on-resistance r onhs1v8 0.27 _ high-side switch current limit i limhs1v8 1.3 1.43 1.6 a low-side switch turn-off current 10 ma rising 94 output-ok (1v8ok) threshold (bit d3 of register 0fh) falling 90 % soft-start rate 1 v/ms lx discharge resistance pwren = gnd 350 _ output-ok (1v8ok) faultblanking time after soft-start done 2m s downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices _______________________________________________________________________________________ 5 electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units ch3 (3v3 step-down converter) output voltage v 3v3fb no load 3.349 3.383 3.416 v operating frequency f 3v3lx 1 mhz load regulation -1.1 %/a line regulation v 3v3in = 3.4v to 14v 0.04 %/v idle-mode trip level (note 4) 150 ma t a = +25? -5 0.01 +5 3v3lx leakage current i 3v3lxlkg v 3v3lx = 0, 14v, v 3v3in = 14v t a = +85? 0.1 ? t a = +25c 0.01 0.1 3v3bst leakage current i 3v 3 bs tlkg v 3v3bst = 5v + v 3v3in t a = +85c 0.1 ? low-side switch on-resistance r onls3v3 0.185 _ high-side switch on-resistance r onhs3v3 0.185 _ high-side switch current limit i limhs3v3 1.8 2 2.2 a low-side switch turn-off current 10 ma rising 94 output-ok (3v3ok) threshold (bit d4 of register 0fh) falling 90 % maximum duty cycle 95 % soft-start rate 1 v/ms lx discharge resistance pwren = gnd 175 _ output-ok (3v3ok) faultblanking time after soft-start done 2m s ch4 (5v0 step-down converter) output voltage v 5v0fb no load 5.000 5.050 5.100 v operating frequency f 5v0lx 1 mhz load regulation -1.25 %/a line regulation v 5v0in = 5.4v to 14v 0.04 %/v idle-mode trip level (note 4) 60 ma t a = +25? -5 +0.01 +5 5v0lx leakage current i 5v0lxlkg v 5v0lx = 0, 14v, v 5v0in = 14v t a = +85? 0.1 ? t a = +25c 0.01 0.1 5v0bst leakage current i 5v 0b s tl kg v 5v0bst = 5v + v 5v0in t a = +85c 0.1 ? low-side switch on-resistance r onls5v0 0.27 _ high-side switch on-resistance r onhs5v0 0.27 _ high-side switch current limit i limhs5v0 1.26 1.4 1.54 a low-side switch turn-off current 10 ma downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 6 _______________________________________________________________________________________ electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units rising 94 output-ok ( 5v 0o k) threshold (bit d5 of register 0fh) falling 90 % s oft- s tar t rate 1 v/ms lx d i schar g e resi stance pwren = gnd 350 _ outp ut- ok ( 5v 0o k) faul t bl anki ng ti m e after s oft- s tar t d one 2m s ch5 (adj step-down converter) quiescent supply current ? (i qlvrpwr + i 5v0fb) + i adjin no switching (ch5 only), v adjfb = 4v, adjsp register = 1fh 65 100 ? output voltage adjust range v adjfb 3 5.067 v operating frequency f adjlx_ 1 mhz output voltage accuracy no load -1 0 +1 % load regulation -0.75 %/a line regulation v adjin = 5.4v to 14v, v adjfb = 4v, adjsp register = 1fh 0.04 %/v idle-mode trip level (note 4) 180 ma t a = +25? -5 0.01 +5 adjlx_ leakage current i adjlx_ v adjlx = 0, 14v, v adjin = 14v t a = +85? 0.1 ? t a = +25? 0.01 0.1 adjbst leakage current i ad jb s tl kg v adjbst = 5v + v adjin t a = +85? 0.1 ? low-side switch on-resistance r onlsadj 0.185 _ high-side switch on-resistance r onhsadj 0.185 _ high-side switch current limit i limhsadj 2.7 3.0 3.3 a low-side switch turn-off current 10 ma rising 94 output-ok (adjok) threshold (bit d6 of register 0fh) falling 90 % soft-start rate 1 v/ms lx discharge resistance adjen = logic 0 (bit d3 of register 07h) 175 _ outp ut- ok ( ad jo k) faul t bl anki ng ti m e after s oft- s tar t d one 2m s ch6 (bst step-up converter) quiescent supply current ? i qlvrpwr + i bstin no switching (ch6 only), bstiv = logic 1(bit d4 of register 09h), v bstfb = 14v, bstvsp register (0ch) = 0fh 100 ? current mode 17.4 33.5 typical output voltage range v bstfb voltage mode (typical dac codes) 12.5 18.7 v overvoltage protection range current mode (typical dac codes) 17.4 36 v overvoltage protection accuracy current mode, v bstfb = 26.7v -3 +3 % downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices _______________________________________________________________________________________ 7 electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units output voltage accuracy v ol tag e m od e, bs tv s p r eg i ster ( 0c h) = 10h -3 +3 % operating frequency f bstlx 667 khz minimum duty cycle 10 % maximum duty cycle 90 93 97 % t a = +25? 31.04 32 32.96 pcs current accuracy i pcs bstcsp register (0bh) = 20h t a = -40? to +85? 30.4 33.6 ma t a = +25? 0.01 1 pcs leakage current i pcslkg v pcs = 0 to lvrin5v t a = +85? 0.1 ? t a = +25? 0.01 5 bstsw leakage current i bstswlkg v b s t s w = 0, v b s t in = 14v , bs te n = l og i c 0 ( b i t d 4 of re g i ster 09h) t a = +85? 0.1 ? t a = +25? 0.01 5 bstlx leakage current i bstlxlkg v bstlx = 0 to 36v t a = +85? 1 ? bstsw switch on-resistance r onbstsw 0.1 _ bstlx switch on-resistance r onbstlx 0.3 _ bstsw switch short-circuitcurrent limit i limbstsw 1.35 a bstlx switch current limit i limbstlx 1.13 a rising, voltage modeonly 95 output voltage ok (bstok)threshold (bit d7 of register0fh) falling, voltage modeonly 90 % soft-start time voltage mode and current mode 4.096 ms bstok fault blanking time aftersoft-start done voltage mode and current mode 1.024 ms ch7 (1v2 step-down converter) output voltage v 1v2fb no load 1.200 1.212 1.224 v operating frequency f 1v2lx 1 mhz load regulation -2.5 %/a line regulation v 1v2in = 3.4v to 14v 0.04 %/v idle-mode trip level (note 4) 200 ma t a = +25? -5 0.01 +5 1v2lx leakage current i 1v2lxlkg v 1v2lx = 0, 14v, v 1v2in = 14v t a = +85? 0.1 ? t a = +25c 0.01 0.1 1v2bst leakage current i 1 v 2 bs tl k g v 1v2bst = 5v + v 1v2in t a = +85c 0.1 ? downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 8 _______________________________________________________________________________________ electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units low-side switch on-resistance r onls1v2 0.185 _ high-side switch on-resistance r onhs1v2 0.27 _ high-side switch current limit i limhs1v2 1.08 1.2 1.32 a low-side switch turn-off current 10 ma rising 94 output-ok (1v2ok) threshold (bit d2 of register0fh) falling 90 % soft-start rate 1 v/ms lx discharge resistance pwren = gnd 175 _ output-ok (1v2ok) faultblanking time after soft-start done 2m s csa (current-sense amplifier) differential input range v cs+ - v cs- v lvrpwr = v cs- = 5.4v to 14v 0 60 mv maximum csout outputcapacitive load c load (note 3) 50 pf csout pulldown resistor r pd 350 k _ bandwidth 150 khz common-mode voltage range v cmr 5.4 14 v common-mode rejection cmr v lvrpwr = v cs- = 5.4v to 14v, v cs+ = v cs- + 24mv 100 db cs_ input current (i cs- + i cs+ )v lvrpwr = v cs- = v cs+ = 5.4v to 13.2v 2 4 a cs+/cs- input-referred offset v iocs gain = 20, v cs+ = v cs- = v lvrpwr = 5.4v to 14v -2.0 0 +2.0 mv v cs+ - v cs- = 48mv, gain = 20 15 v cs+ - v cs- = 24mv, gain = 20 25 csout voltage accuracy v lvrpwr = 5.4v to 14v v cs+ - v cs- = 24mv, gain = 40 15 % csout load current i csout v cs+ - v cs- = 48mv, gain = 20 20 ? rising,csflgen = logic 1 0.912 0.96 1.008 cs flag (bit d1 of register 0dh) (bit d6 of register09h) falling,csflgen = logic 1 0.862 0.91 0.958 v start-up time 60 ? csout clamp voltage v c s ou tc lp 1.215 1.242 1.270 v downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices _______________________________________________________________________________________ 9 electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units gpio logic input/output rising 2.8 gpiopwr uvlo falling 2.5 v rising 0.7 x v gpiopwr input threshold falling 0.25 x v gpiopwr v output-voltage low i gpio_ = -20ma, open-drain output 0.5 v t a = +25? 0.01 0.1 open-drain leakage current v gpio_ = 5.5v t a = +85? 0.1 ? minimum input data setup time t ds 100 ns minimum input data hold time t dh 1 s minimum delay to outputdata valid 5 s input mode 1 m _ pullup resistor from gpio_ togpiopwr v gpiopwr = 5v open-drain outputmode 10 k _ gpio_ pwm clock frequency 244 hz open-drain comparator cmpi input current i cmpi v cmpi = 600mv 0.01 ? cmpi threshold v cmpi rising 1.2125 1.25 1.2875 v cmpi hysteresis v cmpihys 40 mv cmpo delay t cmpo 25mv overdrive 5 s output-voltage low v cmpo i cmpo = -20ma 0.4 v t a = +25? 0.01 1.0 open-drain leakage current i cmpolkg v cmpo = 14v t a = +85? 0.1 ? downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 10 ______________________________________________________________________________________ electrical characteristics (continued)(v _in = 7.2v, ep = gnd, v pwren = 5v, _lx unconnected, c ref = 0.1?; when v _in is specified, it implies all _in pins; t a = -40? to +85?. typical values are at t a = +25?, unless otherwise noted. limits are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and characterization.) parameter symbol conditions min typ max units i 2 c serial input/output and logic logic input low voltage v il 0.8 v logic input high voltage v ih 2.0 v input leakage current i lkg -1 +1 ? output-voltage low v ol i sink = 3ma 0.4 v input/output capacitance c i/o 10 pf serial-clock frequency f scl 400 khz clock low period t low 1.3 ? clock high period t high 0.6 ? bus free time t buf 1.3 ? start setup time t su:sta 0.6 ? start hold time t hd:sta 0.6 ? stop setup time t su:sto 0.6 ? data-in setup time t su:dat 100 ns data-in hold time t hd:dat 0 900 ns receive scl/sda minimum risetime t r (note 5) 20 + 0.1 x c bus ns receive scl/sda maximum risetime t r (note 5) 300 ns receive scl/sda minimum falltime t f (note 5) 20 + 0.1 x c bus ns receive scl/sda maximum falltime t f (note 5) 300 ns transmit sda fall time t f c bus = 400pf 20 + 0.1 x c bus 300 ns pulse width of spike suppressed t sp (note 6) 50 ns sequencer power-up sequencing 1v8 vok to 3v3 start delay 3.6 ms power-down sequencing 3v3 disable to 1v8 disable delay 15 ms 1v8 disable to 1v2 disable delay 15 ms note 3: not tested. design guidance only. note 4: the idle-mode current threshold is the transition point between fixed-frequency pwm operation and idle-mode operation. thespecification is given in terms of output load current for inductor values specified in figure 1. note 5: c bus = total capacitance of one bus line in pf. rise and fall times are measured between 0.1 x v bus and 0.9 x v bus . note 6: input filters on sda and scl suppress noise spikes < 50ns. downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 11 typical operating characteristics (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) reference voltage vs. temperature te m perature ( n c) reference voltage (v) m ax8904 toc01 -40 -15 10 35 60 85 1 . 247 1 . 248 1 . 249 1 . 250 1 . 251 lvrout voltage vs. temperature te m perature ( n c) lvrout voltage (v) m ax8904 toc02 -40 -15 10 35 60 85 5 . 060 5 . 065 5 . 070 5 . 075 5 . 080 shutdown supply current vs. input voltage input voltage (v) shutdown supply current (ua) m ax8904 toc03 24681 01 21 4 0 5 10 15 20 25 30 v pwren = 0v input current vs. input voltage (ch2 + ch3 + ch7 switching, no load) input voltage (v) no-load supply current (ma) m ax8904 toc04 3 6 9 12 15 0 0 . 3 0 . 5 0 . 8 1 . 0 1 . 3 1 . 5 1v2, 1v8, and 3v3 are on input current vs. temperature (ch2 + ch3 + ch7, switching, no load) te m perature ( n c) no-load supply current (ma) m ax8904 toc05 -40 -15 10 35 60 85 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1v2, 1v8, and 3v3 are on startup sequencing waveforms m ax8904 toc06 v pwren 5v/div 0v 3v 0v 0v 0v 0v 2v/div2v/div 2v/div 2v/div v 1v2 v 1v8 v 3v3 v 5v0 2ms/div 1 . 2v 1 . 8v 3 . 3v 5v shutdown sequencing waveforms m ax8904 toc07 v pwren v 1v2 v 1v8 v 3v3 10ms/div 5v/div2v/div 2v/div 2v/div 1 . 2v 0v 0v 0v 0v 1 . 8v 3 . 3v 3v downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 12 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) shutdown sequencing waveforms m ax8904 toc08 v pwren v 3v3 v 5v0 v adj 4ms/div 5v/div2v/div 2v/div 2v/div 5 . 0v 2 . 3v 0v 3v4v 0v 0v 0v efficiency vs. input voltage (1v8) input voltage (v) efficiency (%) m ax8904 toc09 36 91 21 5 70 75 80 85 90 95 100 i out = 600ma efficiency vs. output current (1v8) output current (ma) efficiency (%) m ax8904 toc10 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 1v8 load transient response (10ma to 485ma) m ax8904 toc11 500ma/div50mv/div i out v 1v8 ac ripple 200s/div 485ma 10ma 1v8 load transient response (500ma to 1000ma) m ax8904 toc12 20mv/div500ma/div v 1v8 ac ripple i out 20s/div 1000ma 500ma output voltage load regulation (1v8) output current (ma) output voltage (v) m ax8904 toc13 1 . 70 1 . 74 1 . 78 1 . 82 1 . 86 1 . 90 1 10 100 1000 v in = 7 . 2v v in = 3 . 4v v in = 12v downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 13 typical operating characteristics (continued) (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) efficiency vs. input voltage (3v3) input voltage (v) efficiency (%) m ax8904 toc14 36 9 1 21 5 60 70 80 90 100 i out = 800ma efficiency vs. output current (3v3) output current (ma) efficiency (%) m ax8904 toc15 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10,000 3v3 load transient response (10ma to 625ma) m ax8904 toc16 500ma/div50mv/div i out v 3v3 ac ripple 200s/div 10ma 625ma 3v3 load transient response (625ma to 1250ma) m ax8904 toc17 1a/div20mv/div i out i 3v3 ac ripple 200s/div 625ma 1250ma output voltage load regulation (3v3) output current (ma) output voltage (v) m ax8904 toc18 3 . 28 3 . 32 3 . 36 3 . 40 3 . 44 1 10 100 1000 10,000 v in = 7 . 2v v in = 12v efficiency vs. input voltage (5v0) input voltage (v) efficiency (%) m ax8904 toc19 5 7 9 11 13 15 70 75 80 85 90 95 100 i out = 650ma efficiency vs. output current (5v0) output current (ma) efficiency (%) m ax8904 toc20 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 14 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) 5v0 load transient response (10ma to 400ma) m ax8904x toc21 50mv/div 500ma/div i out v 5v0 ac ripple 200 f s/div 10ma 400ma 5v0 load transient response (400ma to 800ma) m ax8904x toc22 20mv/div 500ma/div i out v 5v0 ac ripple 200s/div 400ma 800ma output voltage load regulation (5v0) output current (ma) output voltage (v) m ax8904 toc23 4 . 92 4 . 97 5 . 02 5 . 07 5 . 12 1 10 100 1000 v in = 5.5v v in = 12v v in = 7.2v efficiency vs. input voltage (adj) input voltage (v) efficiency (%) m ax8904 toc24 5 7 9 11 13 15 70 75 80 85 90 95 100 i out = 1000ma v adj = 4v efficiency vs. output current (adj) output current (ma) efficiency (%) m ax8904 toc25 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10,000 pulse-skipping m ode enabled adj load transient response (200ma to 2000ma to 200ma) m ax8904x toc26 50mv/div 1a/div i out v adj ac ripple 200s/div 200 ma 2000ma adj voltage vs. load current (adj) output current (ma) output voltage (v) m ax8904 toc27 3 . 90 3 . 95 4 . 00 4 . 05 4 . 10 1 10 100 1000 v in = 7 . 2v v in = 12v v in = 5 . 4v downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 15 typical operating characteristics (continued) (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) adj startup response m ax8904x toc28 1a/div 2v/div i out v adj 1ms/div 0v 4v 0a 1a adj shutdown response m ax8904x toc29 1a/div 2v/div i out v adj 1ms/div 0v 0a 4v 1a efficiency vs. led current (bst) led current (ma) efficiency (%) m ax8904 toc30 0 6 12 18 24 30 40 50 60 70 80 90 100 4 leds 6 leds 8 leds led current vs. temperature te m perature ( n c) led current (ma) m ax8904 toc31 -40 -15 10 35 60 85 20 . 20 20 . 25 20 . 30 20 . 35 20 . 40 i led = 20ma bst switching frequency vs. temperature te m perature ( n c) switching frequency ( m hz) m ax8904 toc32 -40 -15 10 35 60 85 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 bst startup response (current mode) m ax8904x toc33 20ma/div 10v/div i led v bst 2s/div 8 wleds 0ma 30ma 0v efficiency vs. input voltage (bst voltage mode) input voltage (v) efficiency (%) m ax8904 toc34 5 7 9 11 13 15 70 75 80 85 90 95 100 v out = 13 . 2v i out = 50ma downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 16 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) efficiency vs. load current (bst voltage mode) load current (ma) efficiency (%) m ax8904 toc35 0 10 20 30 40 50 60 70 80 90 100 11 01 0 0 v out = 13 . 2v bst load transient response (10ma to 60ma, voltage mode) m ax8904x toc36 25ma/div 100mv/div i out v bst ac ripple 200s/div 10ma 60ma bst voltage vs. load current load current (ma) output voltage (v) m ax8904 toc37 13 . 197 13 . 198 13 . 199 13 . 200 13 . 201 13 . 202 13 . 203 1 10 100 v in = 12v v in = 5 . 4v v in = 7 . 2v efficiency vs. input voltage (1v2) input voltage (v) efficiency (%) m ax8904 toc38 3 6 9 12 15 70 75 80 85 90 95 100 i out = 300ma efficiency vs. output current (1v2) output current (ma) efficiency (%) m ax8904 toc39 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 m ax8904 toc40 200ma/div50mv/div i out v 1v2 ac ripple 200 f s/div 1v2 load transient response (1ma to 300ma) 1ma 300ma 1v2 load transient response (300ma to 600ma) m ax8904x toc41 500ma/div20mv/div i out v 1v2 ac ripple 200 f s/div 300ma 600ma downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 17 typical operating characteristics (continued) (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) output voltage load regulation (1v2) output current (ma) output voltage (v) m ax8904 toc42 1 . 18 1 . 20 1 . 22 1 . 24 1 . 26 1 . 28 1 10 100 1000 v in = 7 . 2v v in = 3 . 4v v in = 12v cls startup response (no load) m ax8904x toc43 v clsin i clsin i clsout v clsout 20ms/div 0v 12v 10v/div0v 500ma/div 500ma/div 10v/div c clsout = 2000 f cls startup and shutdown response (425ma load) m ax8904x toc44 v clsin i clsin i clsout v clsout 200ms/div 0v 12v 10v/div0v 500ma/div 500ma/div 10v/div c clsout = 2000 f cls short-circuit protection m ax8904x toc45 v clsout i clsin i clsout 100ms/div v flt 3 . 3v 0v 0v 12v 0ma 0ma 10v/div500ma/div 500ma/div 5v/div open-drain comparator m ax8904x toc46 v c m pi 10 s/div v c m po 0v 0v 0v 7 . 2v 7 . 2v 1 . 3v 1v/div5v/div csout voltage vs. temperature (gain = 20, v cs+ - v cs- = 48mv) te m perature ( n c) csout voltage (v) m ax8904 toc47 -40 -15 10 35 60 85 0 . 925 0 . 930 0 . 935 0 . 940 0 . 945 0 . 950 downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 18 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = 7.2v, v pwren = 3v, shdn unconnected, v adj = 4v, c ref = 0.1?, circuit of figure 1, t a = +25?, unless otherwise noted.) csout voltage vs. temperature (gain = 40, v cs+ - v cs- = 24mv) output voltage (v) m ax8904 toc48 -40 -15 10 35 60 85 0 . 925 0 . 930 0 . 935 0 . 940 0 . 945 0 . 950 te m perature ( n c) csa output voltage vs. input voltage input voltage (v) output voltage (v) m ax8904 toc49 5 7 9 11 13 15 0 . 90 0 . 92 0 . 94 0 . 96 0 . 98 1 . 00 gain = 20v cs+ - v cs- = 48mv csa output voltage vs. input voltage input voltage (v) output voltage (v) m ax8904 toc50 5 7 9 11 13 15 0 . 90 0 . 92 0 . 94 0 . 96 0 . 98 1 . 00 gain = 40v cs+ - v cs- = 24mv overvoltage protection m ax8904 toc51 5v/div5v/div 5v/div 5v/div v ovpwr v ovgate v _in 3 . 3v 12v 12v 14v 14 . 5v v flt 10ms/div reverse-polarity protection m ax8904 toc52 10v/div5v/div 5v/div 100ma/div v ext v rpgate v in i ext 10ms/div 0v 0v 0v -28v m ax8904 toc53 2v/div5v/div 5v/div 5v/div v 5vo v adj v bst 4ms/div shdn functionality v shdn 0v 0v 0v 0v 3v 5v 4v 13 . 2v m ax8904 toc54 5v/div5v/div 5v/div 5v/div v gpio5 v gpio6 v gpio7 2ms/div gpio pwm operation v gpio4 register 05h = 20h register 06h = 40h register 05h = 80h register 06h = 100h downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 19 pin description pin name function 1 csout output voltage of the current-sense amplifier. csout is referenced to analog ground, gnd. its full-scale voltage is 1.2v for 60mv differential input voltage at cs+ and cs-. 2 rpgate external p-mosfet gate control node for reverse polarity protection. internal reverse polarity sensecircuitry controls the gate so that power is applied to the following n-mosfet stage if and only if proper (positive) polarity of power is applied. if reverse polarity input power is applied, the p-mosfet is kept off to protect the n-mosfet stage and the ic. 3 ovpwr supply voltage and overvoltage detection node for the overvoltage protection circuitry. connect ovpwr to system external supply in the absence of reverse polarity protection p-mosfet. when reverse polarity protection p-mosfet is used, connect ovpwr to the source of the reverse polarity protection p-mosfet. 4 ovgate external n-mosfet gate control node for input overvoltage protection. the external n-mosfet is turned on as long as v ovpwr is less than 13.3v. the external n-mosfet is immediately turned off by pulling ovgate low, when v ovpwr exceeds 13.3v, and the ic asserts the flt output. the external n-mosfet is turned back on when v ovpwr falls below ovp threshold. note that the i 2 c interface is always alive, is independent of the overvoltage protection circuit, and turns off only when v lvrout falls below 3.4v. 5 adjbst adj step-down converter boost capacitor connection. connect a 0.1? ceramic capacitor betweenadjbst and adjlx_. 6, 7 adjlx1, adjlx2 adj step-down converter switching node. connect an inductor between adjlx_ and the output ofthe adj converter. connect a 0.1? ceramic capacitor between adjlx_ and adjbst. connect adjlx1 to adjlx2. 8 adjin adj step-down converter supply input. bypass adjin to power ground with a 4.7? ceramiccapacitor. connect adjin to the input power supply node, v in . 9 adjfb ad j s tep - d ow n c onver ter feed b ack inp ut. c onnect tw o 22? or a 47? outp ut cer am i c cap aci tor fr om the outp ut i nd uctor to p ow er g r ound , and r oute the sense tr ace to ad jfb. 10 ref 1.25v reference output. bypass ref to gnd with a 0.1? ceramic capacitor. ref is internally pulledto gnd in shutdown. 11 gnd ground. connect gnd to the ground plane. connect the ground plane with a short wide connectionto the exposed pad (ep). 12 lvrin5v power supply for the internal analog circuitry. it is derived from an internal low-voltage regulatoroutput, lvrout. connect a 10 _ resistor between lvrin5v and lvrout. bypass lvrin5v to gnd with a 1.0? or greater ceramic capacitor. 13 lvrout internal low-voltage regulator output bootstrapped to 5v0 step-down converter output. lvrout is the power supply for the internal drive circuitry. lvrout provides a 5v output when pwren is pulled high. bypass lvrout to power ground with a 1.0? or greater ceramic capacitor. 14 lvrpwr internal 5v low-voltage linear regulator input supply. decouple lvrpwr to power ground with a0.22? or greater ceramic capacitor. connect lvrpwr to the input power-supply node, v in . 15 5v0fb 5v0 step-down converter feedback input. connect a 22? output ceramic capacitor from the outputinductor to power ground, and route the sense trace to 5v0fb. 16 5v0in 5v0 step-down converter input supply. bypass 5v0in to power ground with a 10? ceramic capacitor. connect 5v0in to the input power-supply node, v in . downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 20 ______________________________________________________________________________________ pin description (continued) pin name function 17 5v0lx 5v0 step-down converter switching node. connect an inductor between 5v0lx and the output of the 5v0 converter. connect a 0.1f capacitor between 5v0lx and 5v0bst. 18 5v0bst 5v0 step-down converter boost capacitor connection. connect a 0.1f ce ramic capacitor between 5v0bst and 5v0lx. 19 gpiopwr power supply for gpio inputs and outputs. gpiopwr can be connected to a supply voltage from 3.0v up to 5.5v. correct a 1f ceramic capacitor between gpiopwr and gnd. 20C27 gpio0C gpio7 i 2 c-controlled gpio port. gpio_ can be configured as: ? schmitt-trigger inputs with internal 1m pullup resistor to gpio pwr ? open-drain outputs with internal 10k pullup resistor off-state an d capable of sinking 20ma current from gpiopwr ? open-drain outputs with high-impedance off-state and capable of sinki ng 20ma current from gpiopwr ? high-impedance outputs the default configuration during power-up is schmitt-trigger i nputs until reconfigured through the i 2 c interface. the gpio block has a dedicated power input supply, gpiopwr. the max8904 samples its gpio0 at gpiopwr power-up and selects one of two inte rnal hardwired slave addresses for i 2 c addressing. 28 cmpo active-low, open-drain output of an uncommitted comparator. cmpo can be pulled up to 14v. 29 cmpi comparator input. internal reference voltage is 1.25v. 30 3v3fb 3v3 step-down converter feedback input. connect two 22f or a 47f output ceramic capacitor from the inductor to power ground, and route the sense trace to 3v3fb. the 3v3fb prov ides power to the i 2 c registers. connect the sda and scl pullup resistors to 3v3fb. 31 3v3in 3v3 step-down converter input supply. connect a 4.7f ceramic capacitor between 3v3in and power ground. connect 3v3in to the input power supply node, v in . 32 3v3lx 3v3 step-down converter switching node. connect an inductor between 3v3lx and the output of the 3v3 converter. connect a 0.1f ceramic capacitor between 3v3lx and 3v3bst. 33 3v3bst 3v3 step-down converter boost capacitor connection. connect a 0.1f ce ramic capacitor between 3v3bst and 3v3lx. 34 scl i 2 c serial-clock input 35 sda i 2 c serial-data input/output. data is read on the rising edge of scl. 36 1v2bst 1v2 step-down converter boost capacitor connection. connect a 0.1f ce ramic capacitor between 1v2bst and 1v2lx. 37 1v2lx 1v2 step-down converter switching node. connect an inductor between 1v2lx and the output of the 1v2 converter. connect a 0.1f ceramic capacitor between 1v2lx and 1v2bst. 38 1v2in 1v2 step-down converter input supply. bypass 1v2in to power ground with a 4.7f c eramic capacitor. connect 1v2in to the input power supply node, v in . 39 1v2fb 1v2 step-down converter feedback input. connect two 22f or a 47f output ceramic capacitor from the inductor to power ground, and route sense trace to 1v2fb. 1v2fb is sampled at power-up to determine if the 1v2 step-down converter is used or not. see the poer-up/don sequencing for 1v2, 1v8, 3v3, and 5v0 supplies section. pull 1v2fb to lvrin5v to configure the ic for operation without the 1v2 step-down converter. 40 flt active-low, open-drain fault output. low flt indicates a fault condition. see the fault handling section for details. downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 21 pin description (continued) pin name function 41 shdn shutdown input. when shdn is pulled low, the power converters that are selected in the shutd own register, if currently active, are immediately shut down. the ic recognizes a valid signal on shdn only if 1v2, 1v8, and 3v3 supplies are in regulation. 42 pwren enable input. when pwren is driven high, the lvrout regulator is turned on, and the 1v2, 1v8, 3v3, and 5v0, are turned on with correct sequencing depending on the status of 1v2fb at lvr power-up. when pwren is pulled low, the max8904 turns off all converters and i nternal blocks and goes into low-power standby mode. 43 test test pin. leave as no connection. do not connect power or ground. 44 1v8fb 1v8 step-down converter feedback input. connect a 22f output ceramic ca pacitor from the output inductor to power ground, and route the sense trace to 1v8fb. 45 1v8in 1v8 step-down converter input supply. bypass 1v8in to power ground with a 4.7f c eramic capacitor. connect the 1v8in to the input power supply node, v in . 46 1v8lx 1v8 step-down converter switching node. connect an inductor between 1v8lx and the output of 1v8 converter. connect a 0.1f ceramic capacitor between 1v8lx and 1v8bst . 47 1v8bst 1v8 step-down converter boost capacitor connection. connect a 0.1f ce ramic capacitor between 1v8bst and 1v8lx. 48 bstlx bst open-drain switch node. connect an inductor between bstsw and bstlx . bstlx is high impedance in standby mode. 49 bstsw bst true shutdown switch terminal. connect an inductor between bstsw and bstlx. bypass bstsw to power ground with a 2.2f ceramic capacitor. 50 bstin bst step-up converter supply input. bypass bstin to power ground with a 1f ceramic capacitor. connect bstin to the input power supply node, v in . 51 bstfb bst step-up converter feedback input. connect bstfb to the output cer amic capacitor of the step-up converter. use a 1f capacitor in current regulator mode and use a 10f capaci tor for voltage regulator mode. 52 pcs led current sink. when the bst step-up converter is in current-mode operatio n, connect the cathode of wled string to pcs and the anode of the wled string to the output capacitor. in voltage mode, p cs must be connected to gnd. 53 clsout current-limited switch output. turn on the load switch through the i 2 c interface to connect the switch input, clsin, to the load. 54 clsin current-limited switch input. connect clsin to the input po wer supply node, v in . 55 cs- current-sense amplifier inverting input. connect cs- to the load side of current-sense resistor. 56 cs+ current-sense amplifier noninverting input. connect cs+ to the s upply-side of current-sense resistor. ep exposed pad. power grounds and ground plane must be star-connected to the e p. all large currents from converters flow through the exposed pad that also acts as a h eat sink. a large number of vias are needed to connect ep to board power ground plane. downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 22 ______________________________________________________________________________________ lvrout lvrin5v gnd internal osc 1mhz 10 % thermal flag and shutdown logic center serial i/o, output voltage programming, on/off control, soft-start fault management sda scl 5v0 ref pwren flt ch4 5v0 step-down converter (800ma max) 5v0lx 5v0in 5v0bst 5v0fb c2322 f v in v in v in ch6 bst step-up converter 667khz, 12.8v to 32v, 1.12w output power, i 2 c programmable bstlx bst bstsw bstin 1.25v pcs cmpi cmpo gpio1gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio0 8-bit i 2 c program m able i/o cs+ cs- csout(0 to 1.2v) level shift r215m ? shdn internal chip supply linear regulator bstfb ovp sense, reverse polarity sense and cpump drive ref 5v r1 10 ? gpiopwr c24 4.7 f c22 0.1 f c52.2 f c2 1 f c31 f l6 10 h l110 h 4 to 8 wleds reg2 always on ch1 425ma current limiter clsout v ext 3.4v to 13.2v (+30v/-28v fault protected) load 3v3 or 5v0 lvrin5v clk clk ch7 1v2 step-down converter (600ma max) l2 4.7 h c90.1 f 1v2bst 1v2lx 1v2in c8 2x 22 f c7 4.7 f lvrpwr 5v bootstrap rpgate c1 0.22 f clsin c11680 f q1 q2 v cs+ -v cs- = 0 to 60mv lvrout 1v2fb 1v2 ovgate ovpwr c12 0.1 f v in v in v in ep max8904 3v3 ch3 3v3 step-down converter (1250ma max) 3v3lx 3v3in 3v3bst 3v3fb c202x 22 f c21 4.7 f c19 0.1 f l5 4.3 h v in 1v8 ch2 1v8 step-down converter (975ma max) 1v8lx 1v8in 1v8bst 1v8fb c1722 f c18 4.7 f c16 0.1 f l4 4.7 h v in adj note: 1v2, 1v8, and adj operate in phase. 3v3 and 5v0 operate inphase with respect to each other, but are delayed by 300ns with respect to 1v2, 1v8, and adj. ch5 adj step-down converter (3v to 5.1v i 2 c prog,) (1500ma max rms, 2a pulse) adjlx1 adjin adjbst adjfb c142x 22 f c15 4.7 f c13 0.1 f l3 4.3 h v in adjlx2 v in c41 f c61 f d2 d1 r310 ? c101 f c250.022 f 20 figure 1. typical application circuit and function diagram downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 23 detailed description the max8904 power-management ics provide a com-plete power-supply solution for 2-cell li+ handheld/li-poly applications such as point-of-sale terminals, digital slr cameras, digital video cameras, and ultra-mobile pcs. the max8904 include five step-down converters (1v2- 0.6a, 1v8-0.975a, 3v3-1.25a, 5v0-0.8a, and adj- 1.5a) with internal mosfets and +1%/-3% accurate output voltages for processor core, memory, i/o, and other system power rail requirements. the adj con- verter provides an adjustable output voltage that is 6- bit programmable through the i 2 c interface from 3.0v to 5.1v, in 33.3mv steps.lcd backlighting is supported by a wled boost con- verter that can provide 35ma for up to 8 wleds while operating in the current regulator mode. this boost converter is also configurable as a 6 bit programmable voltage source that can provide up to 63ma of output current. in this voltage mode, the output voltage is 6-bit programmable through the i 2 c interface from 12.5v to 18.7v, in 100mv steps.system input current monitoring for power manage- ment is facilitated by an on-board current sense amplifier (csa) with differential inputs and a 1.2v full scale ground referenced analog output. the csa has an i 2 c programmable gain of 20v/v and 40v/v for full- scale outputs of 4a and 2a, respectively, when usedwith a 15m ? current-sense resistor. a 400khz, i 2 c interface supports output voltage setting of adj power rail and boost regulator (voltage sourcemode), wled current setting for the boost regulator (wled current regulator mode), enable/disable of adj, 5v0, boost regulator, csa and gpio control. the i 2 c interface also enables the host processor to read on-board fault status registers when interrupted by the max8904 flt pin under system fault conditions. an emergency shutdown input, shdn allows converters preselected through i 2 c to turn off immediately, thus saving valuable firmware execution time under powerfail conditions. the max8904 features an 8-bit gpio port controller with pwm capability. the gpio port pins power up as schmitt- trigger cmos inputs. programmable configurations are: schmitt-trigger input with internal 1m ? pullup to gpiopwr open-drain output, with internal 10k ? pullup resis- tor off-state, capable of sinking up to 20ma currentfrom gpiopwr open-drain output with high-impedance state, capa- ble of sinking up to 20ma current from gpiopwr high-impedance output gpio0 can be used to set the i 2 c slave address of the max8904 to either ceh or 8eh (see table 1).a current-limited switch (cls) is provided, with a minimum output current of 425ma, which allows system designers to control input power to external peripheral devices. the max8904 supports input overvoltage protection (ovp) at 13.5v (typ) by controlling an external n-mosfet and reverse polarity protection (down to -28v) of down- stream circuits by controlling an external p-mosfet. an uncommitted, active-low, high voltage open-drain comparator (cmp) with a 1.25v internal reference and 20ma sink current capability that can function as a buzzer driver or can be used for power fail sensing is also provided. the max8904? pwren logic input turns on 1v2, 1v8, 3v3, and 5v0 default power rails. an internal 5v low- voltage linear regulator powered from the input power source provides power for the internal drive and control blocks. when the input is below 5v, the regulator out- put follows the input down to 3.4v. when the input volt- age drops below 3.4v (uvlo), all circuitry except the overvoltage protection block are turned off. when the input voltage drops below 2.85v (ovpwr uvlo), the overvoltage protection block is turned off. i 2 c interface the max8904 internal i 2 c serial interface provides flex- ible control setup, including on/off control of allpower converters (except 1v2, 1v8, and 3v3), cls, csa and cmp, the adj output voltage, the bst output voltage or output current, and the 8-bit gpio port func- tionality. the max8904 internal control and fault status registers are also accessed through the standard bi- directional, 2-wire i 2 c serial interface. the i 2 c serial interface consists of a serial-data line (sda) and a seri-al-clock line (scl) to achieve bidirectional communica- tion between the master and the slave. the max8904 is a slave-only device, relying upon a master to generate a clock signal. the master (typically a microprocessor) initiates data transfer on the bus and generates scl to permit data transfer. the max8904 supports scl clock rates up to 400khz. i 2 c is an open-drain bus. sda and scl require pullup resistors (500 ? or greater). optional resistors (24 ? ) in series with sda and scl protect the device inputs fromhigh-voltage spikes on the bus lines. series resistors also minimize crosstalk and undershoot on bus signals. downloaded from: http:///
i 2 c slave address a bus master initiates communication with max8904 asa slave device by issuing a start condition followed by the max8904 address. as shown in table 1, the max8904 responds to either one of two internally hard- wired slave addresses depending on the gpio0 status when gpiopwr powers up for the first time and exceeds its uvlo (rising) threshold. this address is latched internally and can only be changed if the lvrp- wr voltage is cycled, and the gpiopwr voltage exceeds uvlo again. pullup voltage the max8904 i 2 c interface sda and scl line should use the 3v3 supply as its pullup voltage. start and stop conditions both sda and scl remain high when the serial inter-face is inactive. the master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the max8904, it issues a stop (p) condition by transitioning sda fromlow to high while scl is high. the bus is then free for another transmission (figure 2). both start and stop conditions are generated by the bus master. to send a series of commands to the max8904, the master issues repeated start (sr) commands instead of a stop command to maintain the bus con- trol. in general, a repeated start command is func- tionally equivalent to a regular start command. when a stop condition or incorrect address is detect- ed, the max8904 internally disconnect scl from the bus until the next start condition to minimize digital noise and feedthrough. data transfer each data bit, from the most significant bit to the leastsignificant bit, is transferred one by one during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock. changes in sda while scl is high are control signals (see the start and stop conditions section). each transmit sequence is framed by a start condi-tion and a stop condition. each data packet is nine bits long: eight bits of data followed by an acknowl- edge bit. acknowledge both the i 2 c bus master and the max8904 (slave) gen- erate acknowledge bits when receiving data. theacknowledge bit is the last bit of each nine bit data packet. to generate an acknowledge (a) signal, the receiving device pulls sda low before the rising edge max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 24 ______________________________________________________________________________________ gpio0 status at v gpiopwr > v gpi opwr_uvlo (rising) slave address read slave address write logic 0 (gpio0 pulled down by an internal 100k resistor between gpio0 and gnd) 8fh 8eh logic 1 (gpio0 pulled up by an internal 1m resistor between gpio0 and gpiopwr) cfh ceh table 1. max8904 slave addresses scl sda start condition stop condition repeated start condition start condition t hd, sta t su, sta t hd, sta t buf t su, sto t low t su, dat t hd, dat t high t r t f figure 2. 2-wire serial interface timing detail downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 25 of the acknowledge-related clock pulse (ninth pulse)and keeps it low during the high period of the clock pulse (figure 3). to generate a not-acknowledge (na) signal, the receiving device allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuc- cessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. communication protocols the following i 2 c communication protocols are support- ed by the max8904: writing to a single register writing multiple bytes using register-data pairs reading from a single register reading from sequential registers writing to a single register figure 4 shows the protocol for the master device towrite one byte of data to the max8904. the write byte protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (low). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave updates with the new data 8) the slave acknowledges the data byte. 9) the master sends a stop (p) condition. s scl sda 12 89 not acknowledge (na) acknowledge (a) t hd:dat t su:dat figure 3. acknowledge 1 s number of bits r/nw slave address 7 0 18 register pointer a 1 a 18 data a 1 p 1 slave to master master to slave legend figure 4. write-byte format downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 26 ______________________________________________________________________________________ writing multiple bytes using register-data pairs figure 5 shows the protocol for the master device towrite multiple bytes to the max8904 using register-data pairs. it allows the master to address the slave only once and then send data to multiple registers in a random order. registers may be written continuously until the master issues a stop (p) condition. the write multiple bytes using register-data pairs protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (low). 3) the addressed slave asserts an acknowledge by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a data byte. 7) the slave updates with the new data. 8) the slave acknowledges the data byte. 9) steps 5 to 8 are repeated as many times as the master requires. registers may be accessed inrandom order. 10) the master sends a stop (p) condition. reading from a single register figure 6 shows the protocol for the master device toread one byte of data from the max8904. the read byte protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (low). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start (sr) com- mand. 1 s slave address 7 0 18 register pointer x a 1 a 18 data x a 1 p 1 8 register pointer n a 18 data n a 1 8 register pointer z a 18 data z a 1 slave to master master to slave legend number of bits r/nw number of bits number of bits figure 5. multiple bytes register-data pair format 1 s slave address 7 0 18 register pointer x a 1 a 1 1 sr slave address 7 1 18 data x a 1 na 1 p 1 slave to master master to slave legend r/nw r/nw number of bits figure 6. read-byte format downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 27 7) the master sends the 7-bit slave address followed by a read bit (high). 8) the addressed slave asserts an acknowledge (a) by pulling sda low. 9) the addressed slave places 8-bits of data on the bus from the location specified by the registerpointer. 10) the master asserts a not-acknowledge on the data line to complete operations. 11) the master issues a stop (p) condition. reading from sequential registers figure 7 shows the protocol for reading from sequentialregisters. this protocol is similar to the read byte proto- col except that the master issues an acknowledge to signal the slave that it wants more data. when the mas- ter has all the data, it issues a not-acknowledge (na) and a stop condition (p) to end the transmission. the continuous read from sequential registers protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (low). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer. 5) the slave acknowledges the register pointer. 6) the master sends a repeated start (sr) com- mand. 7) the master sends the 7-bit slave address followed by a read bit (high). 8) the addressed slave asserts an acknowledge by pulling sda low. 9) the addressed slave places 8-bits of data on the bus from the location specified by the registerpointer. 10) the master issues an acknowledge (a) signaling the slave that more data is needed. 11) steps 9 and 10 are repeated as many times as the master requires. following the last byte ofdata, the master issues a not-acknowledge (na) to signal that it wishes to stop receiving data. 12) the master issues a stop (p) condition. 1 1 s slave address 7 0 18 register pointer x a 1 a 1 1 sr slave address 7 1 18 data x a 1 a 1 8 data x + 3 a 1 8 data x + 2 a 1 data x + 1 a 81 8 data n na 1 8 data n - 1 a 1 data n - 2 a 81 p slave to master master to slave legend r/nw r/nw number of bits number of bits number of bits figure 7. read from sequential registers format downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 28 ______________________________________________________________________________________ register a d dr ess r/w por val ue register name d7 d6 d5 d4 d3 d2 d1 d0 00h r/w 00h gpio-a config pwm enable/ disable pwm bank select gpio1 configuration bits pwm enable/ disable pwm bank select gpio0 configuration bits 01h r/w 00h gpio-b config pwm enable/ disable pwm bank select gpio3 configuration bits pwm enable/ disable pwm bank select gpio2 configuration bits 02h r/w 00h gpio-c config pwm enable/ disable pwm bank select gpio5 configuration bits pwm enable/ disable pwm bank select gpio4 configuration bits 03h r/w 00h gpio-d config pwm enable/ disable pwm bank select gpio7 configuration bits pwm enable/ disable pwm bank select gpio6 configuration bits 04h r/w 00h gpio-data i/o-8 i/o-7 i/o-6 i/o-5 i/o-4 i/o-2 i/o-1 i/o-0 05h r/w 00h pwm-bank0 msb lsb 06h r/w 00h pwm-bank1 msb lsb 07h r/w 00h enable csaen x cmpen bsten adjen 5v0en in it clsen 08h r/w 00h shutdown ( shdn ) csa x cmp bst adj 5v0 x cls 09h r/w 00h mode csag c s flge n x bstiv adjm x x ovoff 0ah r/w 00h adjsp lockout x msb lsb 0bh r/w 00h bstcsp x x msb lsb 0ch r/w 00h bstvsp lockout x msb lsb 0dh r 00h fa ult sta tus bs tflt1 bstflt0 vokflt olflt tmp120 x ocin ovin 0eh r 00h overload bstol adjol 5v0ol 3v3ol 1v8ol 1v2ol x clsol 0fh r ffh vok bstok adjok 5v0ok 3v3ok 1v8ok 1v2ok x clsok 10h r device id chip id msb chip id lsb chip rev msb chip rev lsb 11h w 00h clrflts fault status and fault registers are cleared and flt goes to high when clrflts register is set to 01h. fault detection rearms when clrflts is set back to 00h. table 2. register assignments i 2 c accessible registers the i 2 c accessible registers are used to store all the control information from the sda line and configure themax8904 for different operating conditions. recycling power at lvrpwr causes the max8904 to initialize theregisters to their por values. the register assignments of the max8904 are in table 2. downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 29 pwm enable pwm bank gpio configuration gpio configruation description d7/d3 d6/d2 d5/d1 d4/d0 data bits 00 xx gpio-data (04h): 0 = low, 1 = high input with 1m pullup resistor to gpio 01 0 = disabled 1 = enabled 0 = bank01 = bank1 gpio-data (04h): 0 = sink, 1 = pullup open-drain n-device with 10k pullup resistor to gpio, and tolerant of sinking current from 5vpower supply 10 0 = disabled 1 = enabled 0 = bank01 = bank1 gpio-data (04h): 0 = pull, 1 = push open-drain n-device with high-impedancestate, and tolerant of sinking current from 5v power supply 11 xx gpio-data (04h): 0 = hi-z, 1 = hi-z high-impedance (hi-z) output 0 0 0 0 reset value = 0h table 3. gpio configuration register (00h to 03h) d7 d6 d5 d4 d3 d2 d1 d0 data bits io8 io7 io6 io5 io4 io3 io2 io1 reset value = 00h table 4. gpio data register (04h) d7 d6 d5 d4 d3 d2 d1 d0 data bits msb lsb pwm-bank0 msb lsb pwm-bank1 00000000 reset value = 00h table 5. gpio pwm bank register (05h, 06h) gpio configuration register the 00h to 03h registers allow the host processor tosetup gpio0?pio7 configuration through the i 2 c interface. each nibble represents a physical gpio port.these eight nibbles address all the operating require- ments of the 8-bit gpio port, including pwm dimming. led blinking requirement is addressed by turning the leds on and off at the required rate through the i 2 c interface. the least significant two bits of each nibbledefine whether the particular gpio bit is either an input or an output. if it is an output bit, the output device structure (open-drain/pullup, open-drain/high imped- ance, or high impedance/high impedance) is also defined by these two bits. on power-up, the eight gpio bits are configured as inputs. see table 3 for details. gpio data register the gpio data register (04h) is a read/write (r/w) reg-ister that allows the host processor to read those gpio bits that are programmed as inputs and write to those gpio bits that are programmed as outputs through the i 2 c interface. for a read operation, all eight bits are read regardless of whether they are configured as inputs or outputs. it allows the host processor to readstatus of all eight bits. for a write operation, only those bits that are configured as outputs are written to, and the input bits are neglected. on power-up, all gpio bits are configured to inputs by default. each data bit repre- sents a physical gpio port and its functionality is given in table 3. pwm bank register the pwm bank registers pwm-bank0 (05h) and pwm-bank1 (06h) are used to set up two different pulse- width modulation values and switch between them by changing the value of the pwm bank select bit (d6/d2) in the gpio configuration registers (00h to 04h). running at a clocking rate of 244hz, these two regis- ters allow the leds to be driven at 256 discrete levels of intensity control, from 0.0? on/4.1ms off (0%) to 4.084ms on/16? off (99.6%). when multiple leds are controlled by the gpio ports, the use of two pwm reg- isters allows some leds to be dimmed while other leds are simultaneously brightened. individual leds can also be switched between two intensities by tog- gling its pwm-bank assignment. see table 5. downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 30 ______________________________________________________________________________________ d7 d6 d5 d4 d3 d2 d1 d0 reset csaen x cmpen bsten adjen 5v0en init clsen 00h table 6. enable register (07h) d7 d6 d5 d4 d3 d2 d1 d0 reset csa x cmp bst adj 5v0 x cls 00h table 7. shutdown register (08h) enable register with the exception of the 1v2, 1v8, and 3v3 power con-verters, the enable register (table 6) allows the host processor to enable/disable the individual channel when needed. if a bit is programmed to 1, the corre- sponding power converter is enabled; otherwise, with a value of 0, the corresponding power converter remains disabled, even if valid data has been programmed in the associated set point register (0ah, 0bh, or 0ch) for the adj or bst power converter. conversely, if the adjen bit for adj or the bsten bit for bst is set to 1, with a set point register (0ah, 0bh, or 0ch) value of 00h, the adj or bst power converter remains disabled. when the max8904 turns off a particular power con- verter under a fault condition, it sets the corresponding enable register bit to 0. note that the 1v2, 1v8, 3v3, and 5v0 converters are turned on when pwren is pulled high, but the 5v0 con- verter can be turned on/off by the enable register bits once it is above its vok thresholds. the 1v2, 1v8, and 3v3 converters can be turned off only by pulling pwren low. firmware initialization at power-up the max8904 requires a mandatory firmware proce-dure to be executed by the host processor at power-up to initialize the part correctly. the following register writes should be executed before responding to an interrupt on the flt pin of the max8904. 04(h) ? register 07(h) (sets the init bit to 0) 01(h) ? register 11(h) 00(h) ? register 11(h) note that the firmware should keep the init bit set to 0under all operating conditions. firmware initialization for cls operation the max8904 requires a mandatory firmware proce-dure to be executed by the host processor after turning on the cls block to initialize the cls block correctly. the following firmware steps should be executed after turning on the cls block before responding to an interrupt on the flt pin of the max8904: execute a 300ms (min) delay. after the 300ms delay, execute the following register writes: 01(h) ? register 11(h) 00(h) ? register 11(h) shutdown register the shutdown register works in conjunction with shdn to program which converters are turned off in the eventof a power failure. shdn is connected to the midpoint of a resistor-divider from lvrin5v to gnd, and is nomi-nally at 3.3v (see table 7). upon receiving a power-fail signal, the host processor asserts the active-low shdn , and only those power converters whose corresponding bits are programmedto 0 in the shutdown register are turned off, and their associated enable bits in the enable register, if current- ly programmed to 1, are set to 0. the power converters whose bits in the shutdown register are programmed to 1 remain enabled. if a power failure occurs, where the external power source voltage falls below the 3.4v, the max8904 enters the uvlo state. it powers up with default settings when it subsequently comes out of uvlo. note that the host processor can still hold shdn low at this point and it does not cause any action on the max8904. themax8904 performs the shutdown operation only when it detects a high-to-low transition on shdn . note that the 1v2, 1v8, and 3v3 power controllers arealways on and can not be turned off through the shutdown register. downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 31 d7 d6 d5 d4 d3 d2 d1 d0 reset csag csflgen x bstiv adjm x x ovoff 00h table 8. mode register (09h) d7 d6 d5 d4 d3 d2 d1 d0 reset lockout x msb lsb 00h 000000000 0 h table 9. adjsp register (0ah) mode register the mode register is used to configure the operatingmode of various functional blocks. see table 8. csag (bit 7): the max8904 provides a programmable gain current-sense amplifier. the csag bit is used todetermine the gain setting for csa. if it is programmed to 0, the amplifier gain is set to 20v/v. if it is pro- grammed to 1, the amplifier gain is set to 40v/v. csflgen (bit 6): the csflgen bit is used to enable/disable the csa input over-current fault detec-tion feature. if the csflgen bit is high, the max8904 sets the ocin (d1) bit in the fault status register, and asserts flt when an input overcurrent is sensed at csout. the input overcurrent fault detection is dis-abled if csflgen is set to 0. bstiv (bit 4): the bst step-up converter supports voltage mode or current mode operation and the modeselection is realized by the bstiv bit. if it is pro- grammed to 0, the converter operates in the current mode with the bstcsp register setting. if it is pro- grammed to 1, the converter operates in the voltage mode with the bstvsp register setting. adjm (bit 3): the max8904 supports automatic switching from pulse-width modulation (pwm) to pulse-skipping modulation (psm) to improve power supply efficiency at light loads for all of the power converters except the adj step-down converter that must be set by the adjm bit. because the pulse-skipping mode has inherently larger voltage ripple, it may be necessary for the adj supply to remain in pulse-width modulation mode when powering noise sensitive loads such as a gprs radio module. adjm bit allows the host proces- sor to force the adj controller to remain in pwm mode, if desired. when it is programmed to 0, the adj power converter automatically switches between psm and pwm modes. when it is programmed to 1, the power controller is forced to remain in pwm mode. ovoff (bit 0): the ovoff bit is used to turn off the external overvoltage protection n-mosfet, for the pur-pose of battery pack conditioning. when it is programmed to 0, the overvoltage protection circuit determines the stateof the external overvoltage protection n-mosfet. when it is programmed to 1, the overvoltage protection n-mosfet is turned off. adjsp register the max8904 uses the i 2 c interface to set the output voltage of adj power controller. a 6-bit value adjuststhe adj output voltage from 3v to 5.067v, in 33.3mv increments (see table 10). it is an invalid setting if the adjsp register is set as 00h (2.967v). the first valid setting is 01h (3v). see table 9 for the adjsp register definition. table 10 shows hex codes for various output voltage settings of the adj power controller. bit 7 (lockout) of the adjsp register allows the volt- age setting to be programmed only one time after power-up. after power-up, the host processor sets the adjsp value only once. when the host processor changes the 00h setting to a valid number, the max8904 sets the lockout bit to 1. once it is set to 1, subsequent changes to the 6-bit adjsp value are locked out. only by recycling power, the lockout bit can be restored to 0. note that the adjsp register is an r/w register, and it allows the user to read the lockout bit and determine whether the max8904 had already been set to a valid output voltage. when the max8904 detects that the adjen bit is 1, and recognizes valid data in the adjsp register, the adj controller is enabled and soft-starts to the target output voltage. when the enable bit for the adj power converter is set to 1 with an adjsp register value of 00h, the adj stays in the off condition. conversely, with the adjen bit set to 0, the regulator remains disabled, even if valid data has been programmed in the adjsp register. neither of these two conditions generates a flt assertion, since the power converter is considered to be in the off state. fault detection is enabled only ifthe adjen bit is high, and valid data has been pro- grammed in the adjsp register. see table 11. downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 32 ______________________________________________________________________________________ adj voltage hex code adj voltage hex code 3.000 1 4.066 21 3.033 2 4.099 22 3.066 3 4.133 23 3.099 4 4.166 24 3.133 5 4.199 25 3.166 6 4.233 26 3.199 7 4.266 27 3.233 8 4.299 28 3.266 9 4.333 29 3.299 a 4.366 2a 3.333 b 4.399 2b 3.366 c 4.433 2c 3.399 d 4.466 2d 3.433 e 4.499 2e 3.466 f 4.533 2f 3.499 10 4.566 30 3.533 11 4.599 31 3.566 12 4.633 32 3.599 13 4.666 33 3.633 14 4.699 34 3.666 15 4.733 35 3.699 16 4.766 36 3.733 17 4.799 37 3.766 18 4.833 38 3.799 19 4.866 39 3.833 1a 4.899 3a 3.866 1b 4.933 3b 3.899 1c 4.966 3c 3.933 1d 4.999 3d 3.966 1e 5.033 3e 3.999 1f 5.066 3f 4.033 20 table 10. adj output voltage settings adjen bit adjsp valid set point adj enabled fault detection enabled 0 00h no no 0 > 00h no no 1 00h no no 1 > 00h yes yes table 11. adjen/adjsp truth table downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 33 d7 d6 d5 d4 d3 d2 d1 d0 reset value reserved reserved msb l s b 0 0 h xx000000 0 0 h table 12. bstcsp register (0bh) bst current set point register the bst step-up converter has two modes of operation:current and voltage. the current-mode operation is used to drive a wled string, while the voltage-mode operation provides a regulated dc voltage for tft or oled panels. in the current mode, the wled string is connected from the bst output to pcs and the control loop regulates the led current to the value set in the bstcsp register through the i 2 c interface. the bstcsp register (0bh) is defined in table 12. a 6-bit value allows the host proces-sor to adjust the current from 1ma to 63ma, in 1ma mini- mum increments. the maximum recommended increment is 16ma per i 2 c command. it is an invalid setting if the bstcsp register is set to 00h (0ma). thefirst valid number is 01h (1ma). the 3fh setting corre- sponds to 63ma (see table 13 for wled current set- tings and corresponding hex codes). the host processor can change the dimming levels as many times as desired during normal operation. in current mode, the value programmed in the bstvsp register (0ch) is used as an overvoltage threshold. when the output voltage in current mode reaches the threshold, the converter is immediately latched off, and it requires either the host processor to issue either a clrflts command and drive bsten high, or recycling input power to start up again. recommended overvolt- age threshold settings for the led strings are provided in table 14. the overvoltage threshold is programmable from 13.4v to 32v in 300mv increments. a 00h setting in the bstvsp register corresponds to 13.1v and is an invalid setting. a 01h value corresponds to a valid 13.4v overvoltage setting. the host processor can only pro- gram this overvoltage setting in the bstvsp register once, after which the lockout bit is set to 1 to prevent subsequent programming attempts. the one-time pro- grammability of the bstvsp register applies to overvolt- age setting in both current mode and voltage mode. led current (ma) hex code led current (ma) hex code 10 13 32 1 20 23 42 2 30 33 52 3 40 43 62 4 50 53 72 5 60 63 82 6 70 73 92 7 80 84 02 8 90 94 12 9 10 0a 42 2a 11 0b 43 2b 12 0c 44 2c 13 0d 45 2d 14 0e 46 2e 15 0f 47 2f 16 10 48 30 17 11 49 31 18 12 50 32 19 13 51 33 20 14 52 34 21 15 53 35 22 16 54 36 23 17 55 37 24 18 56 38 25 19 57 39 26 1a 58 3a 27 1b 59 3b 28 1c 60 3c 29 1d 61 3d 30 1e 62 3e 31 1f 63 3f 32 20 table 13. bstcsp led current settings no. of series wleds bstvsp setting (v) code in bstvsp register (0ch) 4 18.3 04h 5 22.5 12h 6 26.7 20h 7 30.9 2eh 8 35.1 3ch table 14. overvoltage threshold settings for bst regulator current-mode operation downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 34 ______________________________________________________________________________________ bst voltage set point register when the bst operates in voltage mode, a device suchas a tft or oled display panel can be connected between the bst output and power ground. pcs is connected to gnd in this application to disable the cur- rent sink function. in this mode, the bst acts as a volt- age source with current limit functionality and regulate its output to the value set in the bstvsp register (see table 15). a 6-bit value adjusts the voltage from 12.5v to 18.7v in 100mv increments (see table 16). it is aninvalid setting if the bstvsp register is set to 00h (12.4v). the first valid number is 01h (12.5v). note that with an output of 12.5v, the converter may be operating in dropout for an input voltage of 12.6v. d7 d6 d5 d4 d3 d2 d1 d0 reset lockout reserved msb lsb 0x0000000 0 h table 15. bstvsp register (0ch) ouput voltage (v) hex code output voltage (v) hex code 12.5 01 15.7 21 12.6 02 15.8 22 12.7 03 15.9 23 12.8 04 16 24 12.9 05 16.1 25 13 06 16.2 26 13.1 07 16.3 27 13.2 08 16.4 28 13.3 09 16.5 29 13.4 0a 16.6 2a 13.5 0b 16.7 2b 13.6 0c 16.8 2c 13.7 0d 16.9 2d 13.8 0e 17 2e 13.9 0f 17.1 2f 14 10 17.2 30 14.1 11 17.3 31 14.2 12 17.4 32 14.3 13 17.5 33 14.4 14 17.6 34 14.5 15 17.7 35 14.6 16 17.8 36 14.7 17 17.9 37 14.8 18 18 38 14.9 19 18.1 39 15 1a 18.2 3a 15.1 1b 18.3 3b 15.2 1c 18.4 3c 15.3 1d 18.5 3d table 16. bstvsp voltage settings and hex codes downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 35 bit 7 (lockout) of the bstvsp register allows the volt-age setting to be programmed only one time after power-up. after power-up, the host processor sets the bstvsp value only once. when the host processor changes the 00h setting to a valid number, the max8904 sets lockout bit to 1. once it is set to 1, subsequent changes to the 6-bit bstvsp value are locked out. only by recycling power, the lockout bit can be restored to 0. note that the bstvsp register is an r/w register, and it allows the user to check the lockout bit. in voltage mode, when the max8904 detects that the bsten bit is 1 and recognizes valid data in the bstvsp register, the bst regulator is enabled and soft-starts to the target output voltage. when the bsten is set to 1 with a bstvsp register value of 00h, the bst regulatorstays in the off condition. conversely, with the bsten bit set to 0, the regulator remains disabled, even if the valid data has been programmed in the bstvsp regis- ter. neither of these two conditions generates a flt assertion, since the regulator is considered to be in theoff state. fault detection is enabled only if the bsten bit is high, and valid data has been programmed in the bstvsp register. see table 17. fault handling the max8904 has two fault registers (vok and over-load) and a fault status register (faultstatus). see tables 18, 20, and 21 for details about these register bits. bsten bit bst_sp valid set point bst enabled fault detection enabled 0 00h no no 0 > 00h no no 1 00h no no 1 > 00h yes yes table 17. bsten/bst_sp truth table ouput voltage (v) hex code output voltage (v) hex code 15.4 1e 18.6 3e 15.5 1f 18.7 3f 15.6 20 table 16. bstvsp voltage settings and hex codes (voltage mode) (continued) bstflt1 bstflt0 fault description 0 0 no fault. 0 1 overvoltage (current mode only). 1 0 open or reverse output diode, or open bstfb connection (detected at startup before bstlx switching). 11 pcs short to gnd fault, or bst output short to pcs fault (current mode only, detected at startup beforebstlx switching). table 19. bst fault bit description d7 d6 d5 d4 d3 d2 d1 d0 reset bstol vadjol 5v0ol 3v3ol 1v8ol 1v2ol x clsol 00h table 20. overload register (0eh) d7 d6 d5 d4 d3 d2 d1 d0 reset bstflt1 bstflt0 vokflt olflt tmp120 x ocin ovin 00h table 18. fault status register (0dh) d7 d6 d5 d4 d3 d2 d1 d0 reset bstok vadjok 5v0ok 3v3ok 1v8ok 1v2ok x clsok 11h table 21. vok register (0fh) downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 36 ______________________________________________________________________________________ the max8904 handles faults as outlined in tables 22and 23. the faultstatus register indicates the type of system fault that has occurred. the bstflt0, bstflt1 bits are set based on the type of fault that has occurred in the bst step-up converter (see table 19). the vokflt bit is set when a vok fault has occurred on any one of the power converters. a vok fault occurs either when a converter fails to soft- start or due to overload/short-circuit conditions on the output under normal operation, causing the output volt- age to fall below its vok threshold. the _ok bits in the vok register are set to 1 at power up. when a vok fault occurs, the _ok bit corresponding to the faulty converter is set to 0, indicating a vok fault in the partic-ular converter. the olflt bit is set when the output current on a converter exceeds its overload threshold. the _ol bit in the over- load register corresponding to the faulty converter is set to 1 indicating an overload fault in the particular converter. the tmp120 bit is set when the internal die temperature exceeds +120?. with the current sense resistor across cs+, cs- pins of the max8904 connected in series with the input power source, the ocin bit is set when the csout voltage exceeds its csflag threshold, indicat- ing an input overcurrent condition. the ovin bit is set when the input voltage sensed at the ovpwr pin exceeds the overvoltage threshold. fault type fault response and recovery ? overload on 1v2, 1v8, 3v3 ? vok fault on 1v2, 1v8, 3v3(detected after internal soft-start time plus a 2ms delay). ? flt goes to low, all regulators are turned off immediately after fault detection, and the corresponding bits in faultstatus, overload, and vok registers are set. ? fault detection is enabled for a regulator only if clrflts=00h, and pwren is high. ? toggling pwren (high low high) if pwren is still high, or driving pwren from low to high resets all fault status and fault registers, pulls flt to high, and causes the max8904 to restart the 1v2, 1v8, 3v3, and 5v0 supplies. ? recycling power to the lvrpwr input of the internal linear regulator causes the max8904to power up and remain in standby mode if pwren is low. if pwren is high, the max8904 attempts to start the 1v2, 1v8, 3v3, and 5v0 supplies. ? v clsin -v clsout > 1v, vok fault on the current limited switch atthe end of 250ms soft-start time ? overvoltage, open led fault onled step-up converter (current mode only) ? led cathode (pcs) short toground detected before bstlx switching (current mode only) ? led cathode (pcs) short to ledboost output, detected before bstlx switching (current mode only) ? missing or reversed output diode,open bstfb connection, detected before bstlx switching. ? flt goes to low and the regulator turns off immediately after fault detection. the corresponding bits in faultstatus, overload, and vok registers are set. ? setting clrflts to 01h followed by clrflts to 00h at any time clears all fault registersbits, pulls flt to high, and rearms the max8904 for subsequent fault detection. ? fault detection is enabled for a regulator only if clrflts=00h, and _en=1 (the adj andbst step-up regulators also require valid data to be programmed in the adjsp and bstcsp/bstvsp registers). ? the regulator restarts, fault registers are cleared, flt goes to high, if the _en bit is toggled from 0 to 1. ? toggling pwren (high low high) if pwren is still high, or driving pwren from low to high resets all fault status and fault registers, pulls flt to high, and causes the max8904 to restart the 1v2, 1v8, 3v3, and 5v0 supplies. ? recycling power to the lvrpwr input of the internal linear regulator causes the max8904to power up and remain in standby mode if pwren is low. if pwren is high, the max8904 attempts to start the 1v2, 1v8, 3v3, and 5v0 supplies. table 22. fault handling downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 37 fault type fault response and recovery ? bstfb or led anode shorted to ground (an external 40v-ratedschottky diode must be connected from power ground to bstfb, as close as possible to the bstfb capacitor) ? flt goes to low and bstlx switching stop immediately after fault detection. the corresponding bits in faultstatus, overload registers are set. the bst regulatorturns off 250ms after the fault. ? setting clrflts to 01h followed by clrflts to 00h at any time clears all fault registers bits, pulls flt to high, and rearms the max8904 for subsequent fault detection. ? fault detection is enabled for a regulator only if clrflts = 00h, and bsten = 1. valid data must be programmed in the bstcsp/bstvsp registers). ? the regulator restarts, fault registers are cleared, flt goes to high, if the bsten bit is toggled from 0 to 1. ? toggling pwren (high low high) if pwren is still high, or driving pwren from low to high resets all fault status and fault registers, pulls flt to high, and causes the max8904 to restart the 1v2, 1v8, 3v3, and 5v0 supplies. ? recycling power to the lvrpwr input of the internal linear regulator causes the max8904 to power up and remain in standby mode if pwren is low. if pwren is high, themax8904 attempts to start the 1v2, 1v8, 3v3, and 5v0 supplies. ? overload on 5v0, adj, bst.v clsin -v clsout > 1v, vok fault on the current limiter in normaloperation. ? output voltage < vok fallingthreshold on 5v0, adj, bst (voltage mode only), (detected after soft-start time plus 2ms delay for 5v0, adj, and 1.024ms for bst. ? flt goes to low immediately after fault detection, and fault status and fault registers are set. ? for t flt 250ms, the _en bit is set to 0, and the regulator turns off. ? setting clrflts to 01h followed by clrflts to 00h at any time clears all fault status and fault register bits, pulls flt to high, and rearms the max8904 for subsequent fault detection. ? flt goes to low, fault status and fault register information of a t flt < 250ms momentary fault event is latched until the command of setting clrflts to 01h is issued. ? momentary t flt < 250ms faults do not cause the regulator to turn off. ? fault detection is enabled for a regulator only if clrflts = 00h, and _en = 1. the adj and led boost regulators also require valid data to be programmed in the adjsp andbstcsp or bstvsp registers. ? regulator restarts and fault register and fault status register are cleared, flt goes to high, if the _en bit is toggled (0 to 1). ? toggling pwren (high low high) if pwren is still high, or driving pwren from low to high resets all fault status and fault registers, pulls flt to high, and causes the max8904 to restart the 1v2, 1v8, 3v3, and 5v0 supplies. ? recycling power to the lvrpwr input of the internal linear regulator causes the max8904 to power up and remain in standby mode if pwren is low. if pwren is high, themax8904 attempts to start the 1v2, 1v8, 3v3, and 5v0 supplies. ? input overvoltage at ovpwr ? if an overvoltage event occurs in normal operation, the max8904 turns off the externaln-mosfet through ovgate immediately. ? flt goes to low and ovin goes to 1 in fault status register immediately after fault detection. ? if the input voltage falls below the voltage of v ov - v hys_ov , the ovp n-mosfet turns back on. however, flt stays low and ovin stays high until the max8904 receives the command setting clrflts to 01h. ? setting clrflts to 01h followed by clrflts to 00h at any time clears all fault status andfault register bits, pulls flt to high, and rearms the max8904 for subsequent fault detection. ? if overvoltage persists, the ov n-mosfet remains off, and the max8904 regulator inputsupply decays to 2.85v, and the max8904 turns off at this point. ? if an overvoltage condition occurs at startup, the external ovp n-mosfet does not turn onand the max8904 does not startup. therefore no fault information is stored. table 22. fault handling (continued) downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 38 ______________________________________________________________________________________ fault type actions overload or short circuit on 1v2,1v8, 3v3, 5v0, adj, and bst olflt is set to 1 in the faultstatus register, and corresponding _ol is set to 1 in theoverload register. vok fault on 1v2, 1v8, 3v3, 5v0,adj, bst (voltage mode only), and current limiter vokflt is set to 1 in the faultstatus register, and corresponding _ok is set to 0 in thevok register. overvoltage on bst, open orreversed output diode, open bstfb connection, pcs shorted to ground, pcs shorted to bst output faultstatus register:bstflt1 and bstflt0 are set to 00 if none of the listed faults has occurred. bstflt1 and bstflt0 are set to 01 for overvoltage on bst step-up converter (current mode only). bstflt1 and bstflt0 are set to 10 for open or reversed output diode, or open bstfb connection (detected at startup before bstlx switching). bstflt1 and bstflt0 are set to 11 for pcs shorted to ground or pcs shorted to bst output (current mode only, detected at startup before bstlx switching). input overvoltage fault ovin is set to 1 in the faultstatus register. input overcurrent fault ocin is set to 1 in the faultstatus register for csflgen = 1. +120? overtemperature flag tmp120 is set to 1 in the faultstatus register. table 23. summary of max8904 fault status register and fault register actions d7 d6 d5 d4 d3 d2 d1 d0 chip id msb chip id lsb chip rev msb chip rev lsb read only table 24. device identification register (10h) device identification register device identification register (10h) identifies the chip idand revision, and is shown in table 24. it is a read-only register. clrflts register the max8904 clears all fault registers when the clrfltsregister (11h) is set to 01h, to allow the processor to reset the fault and restart the system. when a fault occurs, the host processor is interrupted and enters itsinterrupt service routine (isr). it masks the interrupt, services the fault by reading the max8904 registers, and may clear the fault(s) to recheck for fault(s) or immediately act upon the faults, and unmasks the inter- rupt. if the fault is still present, the flt signal goes low and the host processor enters its isr again. clrfltsmust be set to 00h to rearm fault detection. fault type fault response and recovery ? 120? overtemperature flag ? the max8904 sets the tmp120 bit in fault status register and pulls flt low if the internal temperature reaches +120? (typ). all converters latch off when the temperature reaches +150? (typ), and the max8904 goes into standby mode. in this mode, the internal linear regulator is turned off and the i 2 c interface is no longer powered. note that pwren may still be held high in this mode. ? toggling pwren (high low high) or recycling max8904 power at lvrpwr allows the max8904 to come out of thermal shutdown. ? input overcurrent ? if csflgen is high, then the ocin bit in the fault status register is set to 1 in the faultstatus register, and flt goes high. if csflgen is low, no action is taken. ? s etti ng c lrflts to 01h fol l ow ed b y c lrflts to 00h at any ti m e cl ear s al l faul t status and faul t r eg i ster b i ts, p ul l s flt to hi g h, and r ear m s the m ax 8904 for sub seq uent faul t d etecti on. table 22. fault handling (continued) downloaded from: http:///
overvoltage and reverse polarity protection the max8904 has an overvoltage protection block asshown in figure 8. this block has its own uvlo thresh- olds, linear regulator, and reference. it essentially oper- ates as a stand-alone overvoltage protection block. applying an external voltage greater than 4v (typ) to ovpwr causes the overvoltage protection block to commence operation. at this time, the external n-mos- fet has not yet been turned on. after a 30ms delay, if the ovpwr voltage is less than 13.65v (typ), the over- voltage charge pump gate drive is powered up and ovgate turns on the external n-mosfet. otherwise, if the ovpwr voltage is greater than 13.65v, ovgate holds the n-mosfet off. after the ovp n-mosfet (q1) powers up, the system voltage v int comes up and powers the internal lvr linear regulator and all power inputs (_in). when v in exceeds the uvlo (rising), the max8904 waits for a logic-high sig-nal on pwren to start up the 1v2, 1v8, 3v3 and 5v0 sup- plies, provided v in is greater than 5.6v (typ). reverse polarity protection down to -28v is provided byuse of an external p-mosfet (q2) to protect downstream circuitry. when the input voltage goes negative, rpgate goes high to turn off the external p-mosfet. when the input voltage rises in the positive direction to a maximumof +30v, rpgate pulls low and turns on the p-mosfet. when an overvoltage event of up to +30v occurs, an internal clamp protects the gate of the p-mosfet from excessive voltage such that the v gate-source voltage of the external p-mosfet (q2) does not exceed 16v (typ). current limited switch the current limited switch (cls) allows the max8904 tocontrol the amount of current that an external device draws from the supply voltage. the cls is connected between the input supply voltage and the target periph- eral device. it provides a pe ripheral current of at least 425ma, and is protected under short-circuit conditions. ashort-circuit condition that lasts greater than 250ms latch- es the cls off. the cls can be enabled and disabled through the enable register and can be selected for immediate power-fail shutdown in the shutdown register. an internal thermal loop protects the cls from an over- load or short-circuit fault that causes excessive power dissipation across the switch. it reduces the current delivered by the cls if the die temperature rises above a preset temperature threshold (+120?) and thus limits the power dissipation in the cls. the thermal loop is enabled only when v clsin - v clsout > 1v. max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 39 dc input ovpwr q2 lvrout lvr overvoltage and reverse polarity sense reg2 5v0fb uvlo ovgate _in pins cs-cs+ bulk capacitor rpgate lvrpwr q1 max8904 v in v int 15m ? figure 8. overvoltage and reverse polarity protection downloaded from: http:///
max8904 with bit clsen in enable register set to 1, the 250mstimer is activated. during normal operation, if v clsin - v clsout > 1v, flt is set, clsok bit is set to 0, the vokflt bit is set to 1, and the 250ms timer is started. ifv clsin - v clsout < 1v before the timer expires, the timer is reset and the ic resumes normal operation. thefault information is preserved and the status of flt , clsok, and vokflt remain unchanged until the i 2 c receives a clrflts command. if v clsin - v clsout > 1v after 250ms, the cls is turned off, flt is asserted, the clsok bit is set to 0, the vokflt bit is set to 1,and the clsen is set to 0. the max8904 needs a clrflts command to clear the fault information in the faultstatus and vok registers and pull flt high. current-sense amplifier the current-sense amplifier measures the differential volt-age across a current-sense resistor and generates an analog voltage proportional to the current-sense resistor differential voltage. this voltage is clamped internally to a maximum of 1.25v. the csa has two programmable-gain settings, 20v/v and 40v/v. when used with a 15m ? cur- rent-sense resistor, it allows full-scale (1.2v) output for 4aand 2a currents, respectively. the csa sets the csaol bit in the overload register if the maximum current is exceeded. the csa can be enabled and disabled through the enable register and can be selected for immediate power-fail shutdown in the shutdown register. open-drain comparator the open-drain comparator (cmp) is an uncommitted,14v open-drain output comparator with 20ma of sinking capability. the cmp can be used for various functions such as independent print-head temperature monitoring, voltage comparison, driving a piezo buzzer, or a 20ma load sinking. the cmp can be enabled and disabled through the enable register and can be selected for immediate power-fail shutdown in the shutdown register. flt interrupt the flt interrupt is an active-low output that indicates any fault condition. the fault condition can be either inter-nal (overtemperature) or external (overloaded output). for certain types of faults such as an overload fault, when flt is driven low, an internal 250ms timer is started. when the timer expires the max8904 disables theaffected power converter. during the 250ms, from the time of the interrupt until the time the converter is dis- abled, the host processor can respond to the interrupt and take an action such as shutting down the powerconverter or some other appropriate action, such as, reducing the load current. for other emergency faults such as an overvoltage fault, there is no 250ms timer related operation, flt is asserted and the converter is immediately turned off. adj step-down converter the adj power converter is an adjustable voltage step-down converter that can be adjusted over a 6-bit range from 3.0v to 5.067v, in 33.3mv increments. the adj power converter is intended to be used for powering var- ious radio modules, such as wi-fi, gprs, and cdma. the adj supply is designed to support a 2a peak and 1.414a rms output current load. an l-c filter may be connected to the output capacitor to attenuate the switching frequency ripple component to within radio module specification. power-up/down sequencing for 1v2, 1v8, 3v3, and 5v0 supplies the pwren signal initiates power-up of the default volt-age rails on the max8904 if lvrpwr (the input of inter- nal linear regulator) exceeds 5.6v (typ). the default power-up rails are 1v2, 1v8, 3v3, and 5v0. if the 1v2 rail is not used, pulling 1v2fb to lvrin5 configures the max8904 to operate without its 1v2 rail, with the corre- sponding power sequencing option. power-down sequencing operates in the reverse sequence of power-up after pwren goes low. figures 9 and 10 show the two power-up/down sequencing cases. table 25 shows the sequencing truth table. the adj and bst supplies can be turned on by the host processor any time after the 3v3 supply reaches its regulation, but all rails and max8904 blocks are shut down when pwren pulls low. note that there is a fixed time delay (d5, 3.6ms, typ) between the 1v8 supply reaching its vok threshold and the 3v3 supply start time. high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 40 ______________________________________________________________________________________ state of 1v2fb during d2 sequencing mode 0 1v2, 1v8, and 3v3 sequenced,followed by 5v0 1 1v8 and 3v3 sequenced, followedby 5v0 table 25. sequencing truth table downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 41 1v2fb 1v8fb 3v3fb 5v0fb pwren lvrin5v d3 d4 d8 d8 d8 d5 d6 d7 adjfb bstfb d2 d_up d_up d_down figure 9. power-up/down sequencing with 1v2 rail used (see table 26 for timing details) d4 d8 d8 d5 d7 d6 1v8fb 3v3fb 5v0fb pwren 1v2fb lvrin5v adjfb bstfb figure 10. power-up/down sequencing without 1v2 rail used (see table 26 for timing details) downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices 42 ______________________________________________________________________________________ applications information inductors for step-down and bst converters the max8904 power converters are optimized to workwith specific values of inductors. either 4.7? or 4.3? inductors should be used for the 1v2, 1v8, 3v3, and adj step-down converters. a 10? inductor should be used for the 5v0 step-down converter. ensure that the inductor saturation current rating exceeds the peak inductor current, and the rated maximum dc inductor current exceeds the maximum output current. for most applications, use an inductor with a dc current rating 1.25 times the maximum required output current. for maximum efficiency, the inductor dc resistance should be as low as possible. a 10? inductor is recommend- ed for the bst step-up converter. see table 27 for rec- ommended inductor specifications. input and output capacitors the input capacitor in a dc-dc converter reduces cur-rent peaks drawn from the input power source and reduces switching noise in the controller. the imped- ance of the input capacitor at the switching frequency should be less than the input source? output imped- ance so that high-frequency switching currents do not pass through the input source. the dc-dc converter output capacitor keeps output ripple small and ensures control-loop stability. the output capacitor must also have low impedance at the switching frequency. ceramic capacitors with x5r or x7r dielectrics arehighly recommended for both input and output capaci- tors due to their small size, low esr, and small temper- ature coefficients. it should be noted that the effective capacitance that can be obtained in ceramic capaci- tors should be derated based on their operating dc bias (maximum converter input voltage in the case of input capacitors and maximum converter output volt- age in the case of output capacitors). see table 27 for recommended capacitor specifications based on the considerations outlined above. cls output capacitor to prevent the max8904 from sensing a startup faultcondition, the maximum capacitance that should be connected to the clsout pin is given by the following equation: c clsout(max) < (425 - i load ) x 225/v clsin(max) where i load is the load current on clsout in ma, v clsin(max) is the maximum input voltage at clsin in volts, and c clsout is in ?. bootstrap capacitors connect a 0.1? low-esr ceramic capacitor betweenthe _lx and _bst for all the step-down converters. the bootstrap capacitor provides the gate-drive voltage for the internal high-side mosfet. x7r or x5r grade dielectrics are recommended due to their stable values over temperature. delay time (m) d2 (response time) < 1 d3 (1v/ms ramp rate) 1.2 d4 (1v/ms ramp rate) 1.8 d5 (fixed delay) 3.6 d6 (1v/ms ramp rate) 3.4 d7 (1v/ms ramp rate) 5 d8 (estimated voltage decay time) 15 d_up (maximum power-up sequence) 11.6 for all supplies, 10m s for 1v2, 1v8, and 3v3 d_down (estimated voltage decay time) 45 table 26. delay time downloaded from: http:///
pcb layout and routing high switching frequencies and relatively large peakcurrents make the pcb layout a very important aspect of power converter design. good design minimizes ground bounce, excessive emi on the feedback paths, and voltage gradients in the ground plane, which can result in instability or regulation errors. a separate low-noise analog ground plane containing the reference, linear regulator, signal ground, and gnd must connect to the power-ground plane at only one point to minimize the effects of power-ground cur-rents. connect gnd to the exposed pad directly under the ic. use multiple tightly spaced vias to the ground plane under the exposed pad to help cool the ic. position the input capacitors from _in to the power ground plane as close as possible to the ic. connect the inductors and output capacitors as close as possi- ble to the ic and keep the traces short, direct, and wide. refer to the max8904 evaluation kit for the rec- ommended pcb layout. max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices ______________________________________________________________________________________ 43 component part number part description l1 toko, de3518 series, 1127as-100m inductor, smt 10?, 20%, 145m dcr, 1.2a l2, l4 toko, de3518 series, 1127as-4r7m inductors, smt 4.7?, 20%, 60m dcr, 1.75a l3, l5 toko, de4518 series, 1124bs-4r3m inductors, smt 4.3?, 20%, 70m dcr, 2.65a l6 toko, de4518 series, 1124bs-100m inductor, smt 10?, 20%, 120m dcr, 1.75a c1 murata, grm188r71c224ka01d ceramic capacitor, 0.22?, 10%, 16v, x7r, 0603 c2, c3, c10 murata, grm188r70j105ka01d ceramic capacitors, 1.0?, 10%, 6.3v, x7r, 0603 c4 taiyo yuden, emk212bj105kg-t ceramic capacitor, 1.0?, 10%, 16v, x7r, 0805 c5 taiyo yuden, emk212bj225kg-t ceramic capacitor, 2.2? 10%, 16v, x7r, 0805 c6 (current mode) taiyo yuden, umk316b7105kl-t ceramic capacitor, 1.0?, 10%, 50v, x7r, 1206 c6 (voltage mode) murata grm32dr61e106ka12l ceramic capacitor, 10?, 10%, 25v, x5r, 1210 c7, c15, c18, c21, c24 taiyo yuden, tmk212bj475kg ceramic capacitors, 4.7?, 10%, 25v, x7r, 0805 c8 taiyo yuden, amk107bj226ma ceramic capacitor, 2 x 22?, 20%, 4v, x5r, 0603 c9, c12, c13, c16, c19, c22 taiyo yuden, emk105b7104kv ceramic capacitors, 0.1?, 10%, 16v, x7r, 0402 c11 sanyo, 16ce680ax electrolytic capacitor, smt 680?, 20%, 16v c14 taiyo yuden, jmk316bj226kl ceramic capacitor, 2 x 22? 10%, 6.3v, x5r, 1206 c17 taiyo yuden, jmk212bj226kg ceramic capacitor, 22?, 10%, 6.3v, x5r, 0805 c20 taiyo yuden, jmk316bj226kl ceramic capacitor, 2 x 22?, 10%, 6.3v, x5r, 1206 c23 taiyo yuden, jmk316bj226kl ceramic capacitor, 22?, 10%, 6.3v, x5r, 1206 c25 taiyo yuden, tmk105b7223kv ceramic capacitor, 0.022?, 10%, 25v, x7r, 0402 d1 on semiconductor, mbr0540t1g schottky diode, 40v, 0.5a, sod123 d2 (the max8904 is protected for short-circuit fault at startup, d2 required only for short-circuit protection in normal operation) on semiconductor, mbr0540t1g schottky diode, 40v, 0.5a, sod123 q1, q2 fairchild semiconductor, fds8962c dual n-/p-mosfets, 30v, 8-pin so r1 yageo, rc0402fr-0710rl resistor, smt 10.0 , 1/16w, 1%, 0402 r2 vishay, wsl1206r0150fea resistor, 0.015 , 1/4w, 1%, 1206 smd r3 (the max8904 is protected for pcs to bstfb short fault at startup, r3 required only for short pcs to bstfb short-circuit protection in normal operation) yageo, rc0402fr-0710rl resistor, smt 10.0 , 1/16w, 1%, 0402 table 27. recommended component specifications (see figure 1) downloaded from: http:///
max8904 high-efficiency power-management ic with i 2 c control for 2-cell li+ battery operated devices maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 44 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package type package code document no. 56 tqfn-ep t5677+2 21-0144 top view max8904 tqfn + 15 1716 18 19 20 21 22 23 24 25 26 27 28 5v0fb 5v0in 5v0lx 5v0bst gpiopwr gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 cmpo cs+ cs- clsin clsout pcs bstfb bstin bstsw bstlx 1v8bst 1v8lx 1v8in 1v8fb test 48 47 46 45 44 4354 5356 55 52 51 50 49 1 2 3 4 5 6 7 8 9 1011121314 42 41 40 39 38 37 36 35 34 33 32 31 30 29 lvrin5v lvrout lvrpwr gnd ref adjfb adjin adjlx2 adjlx1 adjbst ovgate ovpwr rpgate csout 3v3in3v3fb cmpi 3v3lx 3v3bst scl sda 1v2bst 1v2lx 1v2in 1v2fb flt shdn pwren pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . downloaded from: http:///

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